Exemplary embodiments of the present invention relate to a method for fabricating a non-volatile memory device, and more particularly, to a non-volatile memory device having a three-dimensional structure and a vertical channel structure.
A non-volatile memory device retains data even when power is interrupted. As improving the integration density of a memory device having a two-dimensional structure in which memory cells are arranged on a silicon substrate in a single layer becomes more difficult, a non-volatile memory device having a three-dimensional structure in which memory cells are vertically stacked on a silicon substrate has been proposed.
A method for fabricating a conventional non-volatile memory device having a three-dimensional structure will be described below in detail with reference to FIGS. 1A to 1C.
FIGS. 1A to 1C are cross-sectional views illustrating a method for fabricating a conventional non-volatile memory device having a three-dimensional structure. Specifically, FIGS. 1A to 1C illustrate a method for fabricating a non-volatile memory device having a three-dimensional structure in which a cell string is vertically arranged on a substrate. For convenience, FIGS. 1A to 1C focus on a process of forming a plurality of memory cells, and a lower select transistor and an upper select transistor are not illustrated.
Referring to FIG. 1A, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for gate electrodes are alternately formed on a substrate 10 in which a required lower structure, such as a source line and a lower select transistor, is formed. The interlayer dielectric layers 11 and the conductive layers 12 for gate electrodes are selectively etched to form a trench which exposes the surface of the substrate 10. A first material layer 13 in which a charge blocking layer, a charge trap layer, and a tunnel insulation layer are sequentially stacked is formed over the resulting structure in which the trench is formed.
The charge blocking layer serves to block electric charges from passing through the charge trap layer and moving in a direction of a gate electrode. The charge trap layer is used as an actual data storage layer, and traps electric charges into deep-level trap sites or a charge storage layer which stores electric charges within a conduction band according to a data storing scheme. The tunnel insulation layer is provided as an energy barrier layer according to a tunneling of electric charges.
Referring to FIG. 1B, a portion of the first material layer 13 formed on the bottom of the trench is removed to expose the surface of the substrate 10.
In FIG. 1B, reference numeral “13A” represents the first material layer remaining on the inner walls of the trench, where the trench is created for the purpose of subsequently forming a channel.
The removing of the first material layer 13 formed on the bottom of the trench is performed by an etch-back process. However, the first material layer 13A formed on the inner walls of the trench is damaged during the etch-back process (see {circle around (1)} of FIG. 1B). Specifically, the tunnel insulation layer, which is the most influential to the characteristics of the non-volatile memory device, may be damaged. Thus, the data retention characteristic and the cycling characteristic are degraded, causing a reduction in the reliability of the non-volatile memory device.
Referring to FIG. 1C, the trench is filled with a channel layer in order to form a channel 14 protruding vertically from the substrate 10. In this way, a plurality of memory cells stacked along the channel 14 protruding vertically from the substrate 10 are formed.
In this case, since the trench is filled with the layer for a channel in such a state the first material layer 13A is formed along the inner wall of the trench for a channel, the width of the trench for a channel is narrowed and thus void is generated when the trench is filled with the layer for a channel. In addition, since the first material layer 13A and the plurality of memory cells stacked along the channel 14 are integrally connected, the data retention characteristic and the cycling characteristic are further degraded, as a result of filling the void with a channel layer.
During the process of removing a portion of the first material layer 13 formed on the bottom of the trench, the first material layer 13A formed on the inner walls of the trench is damaged, and thus, the data retention characteristic and the cycling characteristic are degraded.
In particular, such concerns may also arise during the process of forming the lower select transistor and the upper select transistor, as well as the process of forming the memory cells.
The lower select transistor and the upper select transistor are formed through the same process as the process of forming the memory cells, however, a gate dielectric layer is formed instead of the first material layer 13. Therefore, the gate dielectric layer formed on the inner walls of the trench may be damaged during the process of removing a portion of the gate dielectric layer formed on the bottom of the trench. Consequently, a threshold voltage of a transistor may be changed and a leakage current may be generated in an off state of the transistor. In particular, when a leakage current is generated, a boosting level in a program inhibited cell string may be lowered and an error may occur during a program operation.